In recent years, with increasing miniaturization or integration of semiconductor integrated circuits (hereinafter called LSIs), the degree of effect that manufacturing variations and variations in process, temperature, voltage, etc. have on delay times has been increasing, and such variations have come to affect manufacturing yields. That is, the growing variations in delay time (hereinafter called “delay variations”) caused by the above-mentioned variations have come to greatly affect the design times and manufacturing yields of LSIs. Accordingly, in the development of an LSI, in order to achieve the desired yield, circuit delay analysis is conducted by calculating signal delay times for the worst-case device variations.
Usually, static timing analysis (STA) is employed for such analysis. In STA, the worst-case signal delay time of the circuit is calculated using the worst-case signal delay time of each device by assuming that every device introduces the worst-case signal delay time.
Generally, in the development of an LSI, the LSI is designed based on circuit cells as logic devices or circuit macro cells and the macro cells have an internal circuit constructed from logic devices. Examples of the circuit cells as logic devices include inverter (NOT logic) circuit cells, AND circuit cells, OR circuit cells, etc., and examples of the circuit cells having internal circuits include D-latch circuit cells, incremental circuit cells, counter circuit cells, etc. Accordingly, in the STA of an LSI, it is standard practice to calculate the worst-case signal delay time of the circuit using the worst-case signal delay time of each circuit cell by assuming that every circuit cell introduces the worst-case signal delay time.
However, with the design method using the STA that assumes the case where every circuit cell introduces the worst-case signal delay time, signal delays tend to be overestimated; accordingly, with increasing miniaturization or integration of LSIs, it has become increasingly difficult to achieve the design that satisfies the desired performance.
Up to now, there is proposed a method that uses a statistical analysis technique, such as Monte Carlo analysis, for calculation of the delay variations caused by manufacturing variations, etc. In this former method, the probability distribution of device signal delay times (hereinafter called the “delay time distribution”) is obtained using Monte Carlo analysis by randomly setting process characteristics such as transistor gate length, etc., and the manufacturing yield is obtained from the delay time distribution. Since the relationship between process variables and delay yields is accurately determined by Monte Carlo analysis, optimum design margins for achieving the desired yield can be obtained.
There is also proposed a method that uses statistical static timing analysis (SSTA), a technique for calculating the delay time distribution of a circuit by statistically handling the signal delay time of each device as a probability distribution, and that obtains the delay time distribution of the circuit by constructing the delay time distribution from the process characteristics such as the gate width of each device, interconnects, etc.
Japanese Laid-open Patent Publication No. 2005-11892 is disclosed. Izumi Nitta, Katsumi Homma, and Toshiyuki Shibuya, “A Study of the Model and the Accuracy of Statistical Timing Analysis,” Technical Report of IEICE, pp. 61-66, December 2005 is disclosed.